The present invention relates to a semiconductor memory device and more specifically to a semiconductor memory device in which a memory cell array is divided into a plurality of blocks.
In a static RAM composed of memory cells arranged in matrix form, where a data is written in or read out of a specific memory cell, a word line is selected by a row decoder and a bit line is selected by a column decoder. In this case, when the word line is selected by the row decoder, transfer gates of all the memory cells connected to the selected word line open. Therefore, in the case where a number of memory cells are connected to a single word line, there exists a problem in that power consumption increases. To reduce the power consumption, the divided word line method has been adopted, in which a word line is divided into several groups to reduce the number of memory cells connected to the single selected word line.
FIG. 4 shows an example of the memory of the above-mentioned method, in which a memory cell array composed of 512 row.times.512 column memory cells is divided into 16 blocks 1 to 16 in the row direction. Further, each row of each block is composed of 32 cells=(4 cell/IO).times.8 , where each row is further divided into 8 I/O units each composed of 4 cells. Further, each of 16 decoders D1 to D16 is provided for each divided block, and a sense amplifier SA is arranged on one side end of the cell array to read data stored in the memory cell array.
FIG. 5 shows a more detailed partial configuration of the memory shown in FIG. 4, in which a memory cell array composed of only one row and two blocks is shown by way of example. One input/output (I/O) unit is composed of 4 memory cells 51, and one of sense amplifiers SA111 to SA118 is provided for each I/O unit. One block is composed of 32 memory cells, and the 32 cells are connected to one word line W101 or W102. The decoder DEC 51 or DEC 52 is a NOR gate for selecting a specific row of a block. That is, a row select line G101 for selecting a row and a block select line B101 or B102 for selecting a block are connected to the input terminals of the decoder DEC 51 or 52, and a word line W101 or W102 is connected to the output terminal thereof, respectively. When the first row is selected by the row select line G101 and the first (left side) block is selected by the block select line B101, the word line W101 changes to a high level to open transfer gates of the memory cells 51 in this first selected block. In this prior-art memory, however, since a single sense amplifier SA must be arranged for each I/O unit composed of 4 memory cells, there exists another problem in that the chip size inevitably increases.
To overcome this problem, a memory device in which a single sense amplifier is used in common for a plurality of blocks has been proposed, as shown in FIG. 6. In this memory device, 8 sense amplifiers are provided for two blocks so as to be usable in common for two blocks via 8 data lines D201 to D208. In this memory device, although the number of sense amplifiers can be reduced, the presence of the data lines D201 to D208 increases the wiring capacitance and therefore the data read speed is reduced. In addition, there exists the other problem in that the chip size increases in the column direction, because the number of data lines D201 to D208 increases with increasing number of bits. In summary, the prior-art semiconductor memory device involves problems in that the chip size increases and the data read speed decreases with increasing number of memory cells.